The present invention relates to an apparatus and a method for efficiently designing a semiconductor integrated circuit.
To produce a semiconductor integrated circuit (LSI), a floor plan is designed based on a netlist obtained through logic synthesizing. Cells are arranged and routed in accordance with the floor plan to layout the circuit in detail. The circuit undergoes simulation to determine whether the layout of the circuit guarantees signal integrity (SI) and power integrity (PI).
The determination of whether the SI or the PI may be guaranteed is performed by determining whether or not an IR drop value (voltage drop value) exceeds a maximum value or by determining whether or not the value of the current flowing through an input/output buffer (hereafter referred to as IO buffer) exceeds a current capacity value. When the SI and PI cannot be guaranteed, the layout of the circuit must be redesigned.
The redesigning increases the design time and raises the design cost. It is thus important that redesigning be decreased.
One reason causing the IR drop value to exceed a maximum value (hereafter referred to as maximum IR drop value) or causing the value of the current flowing through the IO buffer to exceed the current capacity value (hereafter referred to as current capacity) is in that the quantity and locations (provisional quantity and provisional locations) of power supply pads determined through initial designing prior to the detailed routing of the circuit is inappropriate. Thus, in the prior art, the provisional quantity and locations of the power supply pads cannot be accurately determined.
In one prior art example, the provisional quantity and locations of the power supply pads are determined as described below.
(1) Rules are established based on past experience to obtain the quantity of power supply pads required to reduce simultaneous switching noise in an output buffer. The quantity of power supply pads is determined in accordance with the rules.
(2) A clock buffer or the like is adjoined each power supply pad for the noise decrease.
In the prior art, the determination of the provisional quantity and provisional locations of the power supply pads is based on past experience mainly from the viewpoint of countering noise.
Japanese Laid-Out Patent Publication Nos. 11-297840 and 10-294380 describe processes for estimating chip size (more specifically, core size) before laying out the circuitry. In the process described in Japanese Laid-Out Patent Publication No. 11-297840, when predicting the wire length of a core section, factors of a netlist that affect the value of the wire length is not taken into consideration. In the process described in Japanese Laid-Out Patent Publication No. 10-294380, the wire region required around a circuit block is determined from the arrangement of the circuit block.